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nl2tcl-mcp

by collinsoik

Overview

Exposes Yosys synthesis and Icarus Verilog simulation tools to Claude Code for FPGA design workflows.

Installation

Run Command
python server.py

Security Notes

The server includes a TCL validator to block dangerous commands (`exec`, `file delete`, `source`, shell pipes, etc.) when executing Yosys TCL. However, it is susceptible to path traversal vulnerabilities: 1. **Arbitrary File Write:** The `yosys_synthesize` tool's `output_json` argument allows writing to arbitrary file paths if an absolute path or `../` sequence is provided, potentially overwriting system files. 2. **Information Disclosure:** The `list_designs` and `get_design_content` tools' `directory` and `name` arguments can be manipulated with absolute paths or `../` to list or read files outside the intended project directories. No hardcoded secrets or direct network listening are apparent (uses stdio transport).

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Stats

Interest Score0
Security Score6
Cost ClassMedium
Avg Tokens1000
Stars0
Forks0
Last Update2025-12-12

Tags

FPGA DesignVerilog SimulationYosys SynthesisMCP Server